OPTICAL RESIDUE COMPUTING

In the residue number system (RNS) an integer is represented as a set of residues with respect to a set of moduli. Such RNS system can perform arithmetic such as addition, which is executed digit-by-digit; a large number is decomposed by factorization using the moduli as basis functions, which allows for parallelism. The built-in parallelism of bosonic photons allow mapping RNS-based arithmetic onto photonic on-chip, enabling highly parallel optical compute engines. Here we investigate an photonic RNS adder deploying parallel waveguides, and 2x2 hybrid photonic-plasmonic ITO switches. Allowing each switch to be individually reconfigured, via a control signal. This enables a crossbar-like spatial light router, where the residue is represented by spatially shifting the input waveguides relative to the routers outputs. We show that this nanophotonic modulo-5 system adder consumes 7.2 fJ/bit, occupying 200 um^2 of footprint, and having a response time of about 5 ps mainly dominated by the drivers setup time. RNS adders could be beneficial for convolution information processing.
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REPROGRAMMABLE OPTICAL COMPUTER IN PHOTONICS




​Partial Differential Equations (PDE) are ubiquitous to science and engineering due to their ability to formulate multi-variable phenomena such as diffusions, electrostatics, aerodynamics and quantum mechanics. As a precise way of predigesting continuous physical problems analogously, PDEs are capable of converging into an error-inclusive PDE solution with their inaccuracy subject to the discretization step limited by computing budget. Brute-force methods in solving PDEs numerically using today’s electrical computing systems do not scale well with problem dimension and power consumption and compute run-time due to their iterative nature, thus severely/fundamentally limiting their utilization . Here, we propose a photonic network solution to emulate and approximately solve PDE problems (Laplace equation) in the optical domain Reprogrammable optical computer (Roc). The distributed network mimic a resistive network which solves the PDE by finite differences.




REPROGRAMMABLE OPTICAL COMPUTER IN METATRONICS
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We also demonstrate the implementation of a nano-optic co-processor able to solve partial differential equation based on a metatronic nanocircuit board.  We propose a nano-optic circuit based on air groove meshes, engraved in a epsilon-near-zero loss-less substrate, aiming to map a finite difference mesh similarly to a network of resistors. 
Thanks to a unprecedented control of the ENZ and material losses over ITO, we also explore the possibility to implement the sub-wavelength circuit using opportunely processed Indium Tin Oxide films. Here we use different deposition conditions, in order to tune the ENZ position, which potentially leads to a top-down monolithically integrated circuit. The elements of the circuit could then be electrostatically tuned, thus allowing for the processor to be re-programmable , aiming to solve a variety of PDEs including Laplace Equation, Poisson Equation, Diffusion Equation, and the Wave Equation, by introducing optical capacitance and inductance.
Due to the confinement of the displacement current in the air grooves, the impedances are locally coupled, which in terms of electrical circuit means that the Norton/Thevenin equivalents are admissible obtaining same results as electrical network.

OPTICAL COPROCESSOR FOR REAL TIME PROBABILISTIC AND CRYPTOGRAPHIC COMPUTING 

We introduce a low-power programmable optical convolution coprocessor based on a 4F system able to perform one-shot O(n) convolutions between a large matrix (1920x1080, 8-bit) and a signature, with a bandwidth of 1kHz (Fig. 1). The proposed accelerator exploits Fourier optics and it leverages the wave-nature of low power coherent light and the high density of information that can carry. This project explores one-shot efficient execution of large modular multiplication and convolutions optically with nanosecond-short delays and retaining high-degree of reconfigurability (‘mask’=SLM/DMD, SLM = spatial light modulator, DMD = digital mirror display. Both are examples of digital light processing (DPL)) using high-speed interface with an FPGA to handle high data volumes.
In brief we will i) develop a Gen-1 prototype, ii) built and test a Gen-1* enhanced fully functional modulator multiplication for CNN and other operations, and iii) pre-prototype a Gen-2 system exploiting emerging GHz-fast SLM technology based on nano-optical enhanced nonlinearity (e.g. metasurfaces) and Metalenses for micrometer providing ultimate throughput at miniscule footprints compared to COTS systems to-date. Considering a naïve O(MNkk) algorithm complexity for performing convolutions,a ‘raw’ performance assessment, of the explored Gen1&1* systems of this project shows  a near-HPC like computing capability with up to 250+TMac/s in Gen-1 and 3+PMAC/s in Gen-1* throughputs (20x improvement over best GPU’s) with 0.1-1ms-short reconfigurable timescales at 50W total system power and footprints comparable (Gen-1*) to today’s GPUs. Aiming to explore the limit of information density (MAC/s) in optics, we will trade the bulky and slow component of Gen-1* with metalenses and reprogrammable metasurfaces, and we will design a second generation of our coprocessor (Gen-2) that will enable computing capability in the sub-ns regime, towards real time.

PHOTONIC FAST FOURIER TRANSFORM

The fast Fourier transform (FFT) is a useful and prevalent algorithm in signal processing. It characterizes the spectral components of a signal, or is used in combination with other operations to perform more complex computations such as filtering, convolution, and correlation. Digital FFTs are limited in speed by the necessity of moving charge within logic gates. An analog temporal FFT in fiber optics has been demonstrated with highest data bandwidth. However, the implementation with discrete fiber optic FFT components is bulky. Here, we present and analyze a design of an optical FFT in Silicon photonics and evaluate its performance with respect to variations in phase and amplitude. We discuss the impact of the deployed devices on the FFT’s transfer function quality as defined by the transmission output power as a function of frequency, detuning phase, optical delay, and loss.

Convolutional neural networks have become an essential element of spatial deep learning systems. In the prevailing architecture, the convolution operation is performed with Fast Fourier Transforms (FFT) electronically in GPUs. The parallelism of GPUs provides an efficiency over CPUs, however both approaches being electronic are bound by the speed and power limits of the interconnect delay inside the circuits. Here we present a silicon photonics based architecture for convolutional neural networks that harnesses the phase property of light to perform FFTs efficiently. Our all-optical FFT is based on nested Mach-Zender Interferometers, directional couplers, and phase shifters, with backend electro-optic modulators for sampling. The FFT delay depends only on the propagation delay of the optical signal through the silicon photonics structures. Designing and analyzing the performance of a convolutional neural network deployed with our on-chip optical FFT, we find 100x improvements compared to GPUs when exploring a compounded figure-of-merit given by power per convolution over volume. This performance is enabled by mapping the desired mathematical function, an FFT, synergistically onto hardware, in this case optical delay interferometers.

PHOTONIC DIGITAL TO ANALOG CONVERTER

Digital-to-analog converters (DAC) are indispensable functional units in signal processing instrumentation and wide-band telecommunication links for both civil and military applications. In photonic systems capable of high data throughput and short delay, a commonly found system limitation stems from the electronic DAC due to the delay in sub-micron CMOS architectures and E-O conversions. A photonic DAC, in contrast, directly converts electrical digital signal to optical analog one with high speed and low energy consumption. Here, we introduce a novel parallel photonic DAC along with an experimentally demonstration of a 4-bit passive iteration of DAC. The design guarantees a linear intensity weighting functionality with a 50Gs/s and much smaller footprint compares to any other proposed photonics DACs. This design could be potentially implemented into novel photonic integrated neuromorphic computing engines for next generation label processing and edge computing platforms.